Static Random Access Memory (SRAM) is widely used in integrated circuits. SRAM cells stores data in latches that are formed of two P-type Metal-Oxide-Semiconductor (PMOS) devices and two N-type Metal-Oxide-Semiconductor (NMOS) devices. SRAMs have many designs including, for example, Six-Transistor (6T) SRAMs, Eight-Transistor (8T) SRAMs, single-port SRAMs, two-port SRAMs, dual-port SRAMs, and the like. An SRAM may be referred to as a two/dual port SRAM, indicating that the SRAM may be a two-port SRAM or a dual-port SRAM.
Conventionally, 8T SRAMs with two/dual ports are operated with two clock signals, one for read/write operations, and one for write/read operations. The two clock signals are independent from each other. Although the performance of the two/dual portion 8T SRAMs is high due to the fact the that the two clock signals may be tuned independently from each other, the chip area occupied by the two/dual port 8T SRAMs is high. Accordingly, pseudo two-/dual-port 6T SRAMs were designed.
The sizes of the 6T SRAMs are smaller compared to two/dual port 8T SRAMs. For example, the chip area occupied by 8T SRAMs may be 1.5 times the chip area occupied by 6T SRAMs. Due to structure limitations, the 6T SRAMs use one clock signal for both read operations and write operations, wherein the rising edges of the clock signal are used for read operations, and the falling edges of the clock signal are used for write operations, or vice versa.
The performance of the pseudo two/dual port 6T SRAMs, however, is limited. This is because the read operations and the write operations are tied together, and the clock cycle time has to be long enough to accommodate the one of the read and write operations that takes longer time to finish. Hence, it is difficult to tune the performance of pseudo two-/dual port 6T SRAMs.